Verilog code for logic gates

Design Code:

module and1(a,b,c);

    input a,b;

    output c;

    assign c=a & b;

endmodule

Testbench Code:

module tb;

    reg a1,b1;

   wire c1;

    and1 tess(a1,b1,c1);

    initial begin

  $dumpfile("dump.vcd");

  $dumpvars(1);

     $display("input & outputs");

    a1=1'b0;

    b1=1'b0;

    #1

    $display("a=%b, b=%b : c=%b",a1,b1,c1);

    a1=1'b0;

    b1=1'b1;

    #1

    $display("a=%b, b=%b : c=%b",a1,b1,c1);

    a1=1'b1;

    b1=1'b0;

    #1

    $display("a=%b, b=%b : c=%b",a1,b1,c1);

    a1=1'b1;

    b1=1'b1;

    #1

    $display("a=%b, b=%b : c=%b",a1,b1,c1);

    end

endmodule 

Note: You can test this code  in virtual mode also at https://www.edaplayground.com/  free of cost by login with the college mail/ office mail.

There you need to paste 1. Source code in design side (R.H.S)

                                       2. Test Bench code in test side (L.H.S)

Also, simple settings to observe the outputs in edaplayground.com are

--> Testbench + Design should be selected with Systemverilog/ verilog

--> Tools & Simulators can be Icarus Verilog 0.9.7 or any one there, which supports.

--> In Tools & Simulators, Open EPWave after run is to be marked to observe wave forms.

You can observe outputs in Log window below

Outputs For this example:

input & outputs
a=0, b=0 : c=0
a=0, b=1 : c=0
a=1, b=0 : c=0

a=1, b=1 : c=1  

Waveforms :

Note: 

 

1. Here logical and  gate is taken into consideration, this can be valid even for remaining logic gates also.

  you can replace and symbol with the respective symbol for other logic gates in assign c=a & b;

2. For or gate, Symbol is |

3. For ex-or gate, Symbol is ^