Design Code:
module fa1(a,b,c,s,cy);
input a,b,c;
output s,cy;
assign s = a ^ b ^ c;
assign cy = (a & b) | (b & c) |(c & a);
endmodule
Testbench Code:
module tb;
reg a1,b1,c1;
wire s1, cy1;
fa1 tess(a1,b1,c1,s1,cy1);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
$display("input & outputs");
a1=1'b0;
b1=1'b0;
c1=1'b0;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
a1=1'b0;
b1=1'b0;
c1=1'b1;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
a1=1'b0;
b1=1'b1;
c1=1'b0;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
a1=1'b0;
b1=1'b1;
c1=1'b1;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
a1=1'b1;
b1=1'b0;
c1=1'b0;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
a1=1'b1;
b1=1'b0;
c1=1'b1;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
a1=1'b1;
b1=1'b1;
c1=1'b0;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
a1=1'b1;
b1=1'b1;
c1=1'b1;
#1
$display("a=%b, b=%b c=%b: s=%b cy=%b",a1,b1,c1,s1,cy1);
end
endmodule
Note: You can test this code in virtual mode also at https://www.edaplayground.com/ free of cost by login with the college mail/ office mail.
There you need to paste 1. Source code in design side (R.H.S)
2. Test Bench code in test side (L.H.S)
Also, simple settings to observe the outputs in edaplayground.com are
--> Testbench + Design should be selected with Systemverilog/ verilog
--> Tools & Simulators can be Icarus Verilog 0.9.7 or any one there, which supports.
--> In Tools & Simulators, Open EPWave after run is to be marked to observe wave forms.
You can observe outputs in Log window below
a=0, b=0 c=0: s=0 cy=0
a=0, b=0 c=1: s=1 cy=0
a=0, b=1 c=0: s=1 cy=0
a=0, b=1 c=1: s=0 cy=1
a=1, b=0 c=0: s=1 cy=0
a=1, b=0 c=1: s=0 cy=1
a=1, b=1 c=0: s=0 cy=1
a=1, b=1 c=1: s=1 cy=1
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